library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.global_definition.all;

architecture behave of pc is
begin
    proc_pc : process(clk, rst_n)
        variable pc_temp : std_ulogic_vector(width-1 downto 0);
    begin
        if rst_n = '0' then
            pc_temp := (others => '0');
        elsif RISING_EDGE(clk) then
            if pc_enable = '1' then
                pc_temp := pc_in;
            end if;
        end if;
        pc_out <= pc_temp;
    end process;
end behave;
